 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| LH5164AZ8 FEATURES * 8,192 x 8 bit organization * Access time: 200 ns (VCC = 3.0 V MAX.) * Power consumption: Operating: 60 mW (MAX.) @ 3 V Standby (to 60C): 3 W (MAX.) @ 3 V Data hold 0.6 A (VCC = 3 V, TA = 60C) * Operating voltage range: 3.0 V to 3.6 V * Wide operating temperature range: -30 to 60C * Fully-static operation * TTL compatible I/O * Three-state outputs * Package: 28-pin, 450-mil SOP CMOS 64K (8K x 8) Static RAM DESCRIPTION The LH5164AZ8 is a static RAM organized as 8,192 x 8 bits. It is fabricated using silicon-gate CMOS process technology. PIN CONNECTIONS 28-PIN SOP NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE CE2 A8 A9 A11 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 5164AZ8-1 TOP VIEW Figure 1. Pin Connections for SOP Package 1 LH5164AZ8 CMOS 64K (8K x 8) Static RAM ROW ADDRESS BUFFERS ROW SELECT A9 24 A8 25 A12 2 A7 3 A6 4 A5 5 A4 6 A3 7 MEMORY ARRAY (256 x 256) 28 VCC 14 GND I/O1 11 I/O2 12 I/O3 13 I/O4 15 I/O5 16 I/O6 17 I/O7 18 I/O8 19 INPUT DATA CONTROL COLUMN I/O CIRCUITS COLUMN SELECT COLUMN ADDRESS BUFFERS WE 27 OE 22 CE2 26 CE1 20 8 A2 9 A1 10 A0 23 A11 21 A10 5164AZ8-2 Figure 2. LH5164AZ8 Block Diagram PIN DESCRIPTION SIGNAL PIN NAME SIGNAL PIN NAME A0 - A12 CE1 - CE2 WE OE Address inputs Chip Enable input Write Enable input Output Enable input I/O1 - I/O8 VCC GND NC Data inputs and outputs Power supply Ground Non connection 2 CMOS 64K (8K x 8) Static RAM LH5164AZ8 TRUTH TABLE CE1 CE2 WE OE MODE I/O1 - I/O8 SUPPLY CURRENT NOTE H X L L L NOTE: 1. X = H or L X L H H H X X L H H X X X L H Standby Standby Write Read Output deselect High-Z High-Z DIN DOUT High-Z Standby (ISB ) Standby (ISB ) Operating (ICC) Operating (ICC) Operating (ICC) 1 1 1 ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT NOTE Supply voltage Input voltage Operating temperature Storage temperature VCC VIN Topr Tstg -0.3 to +7.0 -0.3 to VCC + 0.3 -30 to +60 -65 to +150 V V C C 1 1 NOTE: 1. The maximum applicable voltage on any pin with respect to GND. RECOMMENDED OPERATING CONDITIONS (TA = -30 to +60C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT Supply voltage Input voltage (VCC = 3.0 to 3.6 V) VCC VIH VIL 3.0 VCC - 0.5 -0.3 3.6 VCC + 0.3 0.2 V V V DC CHARACTERISTICS (TA = -30 to +60C, VCC = 3.0 to 3.6 V) ADD TABLE NOTE: 1. CE2 should be VCC - 0.2 V or 0.2 V. 3 LH5164AZ8 CMOS 64K (8K x 8) Static RAM AC CHARACTERISTICS (1) READ CYCLE (TA = -30 to +60C, VCC = 3.0 to 3.6 V) PARAMETER SYMBOL MIN. MAX. UNIT Read cycle Address access time Chip enable access time (CE1) (CE2) tRC tAA tACE1 tACE2 tOE tOH (CE1) (CE2) (CE1) (CE2) tLZ1 tLZ2 tOLZ tHZ1 tHZ2 tOHZ 200 200 200 200 150 10 20 20 10 0 0 0 60 60 40 ns ns ns ns ns ns ns ns ns ns ns ns Output enable access time Output hold time Chip enable to output in Low-Z Output enable to output in Low-Z Chip enable to output in High-Z Output disable to output in High-Z (2) WRITE CYCLE (TA = -30 to +60C, VCC = 3.0 to 3.6 V) PARAMETER SYMBOL MIN. MAX. UNIT Write cycle time Chip enable to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time Output active from end of write WE to output in High-Z OE to output in High-Z tWC tCW tAW tAS tWP tWR tDW tDH tOW tWZ tOHZ 200 180 180 0 150 0 100 0 20 0 0 60 40 ns ns ns ns ns ns ns ns ns ns ns AC TEST CONDITIONS PARAMETER MODE Input voltage amplitude Input rise/fall time Timing reference level Output load conditions 0 to VCC 10 ns 1.5 V No load CAPACITANCE (TA = 25C, f = 1 MHz) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT Input capacitance Input/output capacitance CIN CI/O VIN = 0 V VI/O = 0 V 7 10 pF pF NOTE: This parameter is sampled and not production tested. 4 CMOS 64K (8K x 8) Static RAM LH5164AZ8 DATA RETENTION CHARACTERISTICS (TA = -30 to +60C) PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE Data retention supply voltage Data retention supply current Chip disable to data retention Recovery time VCCDR ICCDR tCDR tR CE2 0.2 V or CE1 VCCDR - 0.2 V VCCDR = 3.0 V, CE2 0.2 V or CE1 VCCDR - 0.2 V TA = 25C TA = 60C 2.0 5.5 0.2 0.6 V A ns ns 1 1 0 tRC 2 NOTES: 1. CE2 should be VCCDR - 0.2 V or 0.2 V. 2. t RC = Read cycle time tRC ADDRESS tAA tACE1 CE1 tLZ1 tACE2 tHZ1 CE2 tLZ2 tOE tOLZ tHZ2 OE tOHZ tOH DOUT NOTE: WE is "HIGH" level during the read cycle. DATA VALID 5164AZ8-3 Figure 3. Read Cycle 5 LH5164AZ8 CMOS 64K (8K x 8) Static RAM tWC ADDRESS OE tAW tCW (NOTE 2) CE1 tCW tWR tWR (NOTE 4) CE2 tAS (NOTE 3) WE tOHZ tWP (NOTE 1) tWR DOUT tDW (NOTE 5) tDH DIN DATA VALID NOTES: 1. The writing occurs during an overlapping period of CE1 = "LOW," CE2 = "HIGH," and WE = "LOW" (tWP). 2. tCW is defined as the time from the last occuring transit, either CE1 LOW transit or CE2 HIGH transit, to the time when the writing is finished. 3. tAS is defined as the time from address change to writing start. 4. tWR is defined as the time from writing finish to address change. 5. The input signals of opposite phase to the outputs must not be applied while I/O pins are in the output state. 5164AZ8-4 Figure 4. Write Cycle 6 CMOS 64K (8K x 8) Static RAM LH5164AZ8 tWC ADDRESS tAW tCW (NOTE 2) CE1 tCW tWR tWR (NOTE 4) CE2 tAS (NOTE 3) WE tWZ (NOTE 6) DOUT tDW (NOTE 5) DIN DATA VALID tWP (NOTE 1) tWR tOW (NOTE 7) tDH NOTES: 1. The writing occurs during an overlapping period of CE1 = "LOW," CE2 = "HIGH," and WE = "LOW" (tWP). 2. tCW is defined as the time from the last occuring transit, either CE1 LOW transit or CE2 HIGH transit, to the time when the writing is finished. 3. tAS is defined as the time from address change to writing start. 4. tWR is defined as the time from writing finish to address change. 5. The input signals of opposite phase to the outputs must not be applied while I/O pins are in the output state. 6. If CE1 LOW transit or CE2 HIGH transit occurs at the same time or after WE LOW transit, the output will remain high-impedance. 7. If CE1 HIGH transit or CE2 LOW transit occurs at the same time or before WE HIGH transit, the output will remain high-impedance. 5164AZ8-5 Figure 5. OE Low Fixed 7 LH5164AZ8 CMOS 64K (8K x 8) Static RAM CE1 CONTROL (NOTE) VCC 2.5 V tCDR DATA HOLD MODE tRDR VCC - 0.2 V VCCDR CE1 0V CE1 VCCDR - 0.2 V CE2 CONTROL DATA HOLD MODE VCC 2.5 V CE2 tCDR tRDR VCCDR 0.2 V 0V CE2 0.2 V NOTE: To control the data hold mode at CE1, fix the input level of CE2 between VCCDR to VCCDR - 0.2 V or 0 V to 0.2 V during the data hold mode. 5164AZ8-6 Figure 6. Low Voltage Data Retention 8 CMOS 64K (8K x 8) Static RAM LH5164AZ8 PACKAGE DIAGRAM 28SOP (SOP028-P-0450) 1.27 [0.050] TYP. 1.70 [0.067] 15 8.80 [0.346] 8.40 [0.331] 12.40 [0.488] 11.60 [0.457] 0.50 [0.020] 0.30 [0.012] 28 10.60 [0.417] 1 18.20 [0.717] 17.80 [0.701] 14 1.70 [0.067] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.025 [0.040] 2.40 [0.094] 2.00 [0.079] 0.20 [0.008] 0.00 [0.000] 1.025 [0.040] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 28SOP 28-pin, 450-mil SOP ORDERING INFORMATION LH5164AZ8 Device Type CMOS 64K (8K x 8) Static RAM Example: LH5164AZ8 (CMOS 64K (8K x 8) Static RAM, 200 ns, 28-pin, 450-mil SOP) 5164AZ8-7 9 |
Price & Availability of LH5164AZ8
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |